(1) Field of the Invention
The invention relates to the general field of thin film deposition with particular reference to contact resistance between films.
(2) Description of the Prior Art
As a member of the general class of materials known as valve metals, a freshly formed silicon surface will rapidly develop a layer of native oxide when exposed to a source of oxygen. The growth of such a layer is self limiting, terminating at about 25 Angstroms for silicon at room temperature.
In the course of manufacturing silicon integrated circuits, electrical contact needs to be made to various silicon surfaces, some being part of the original single crystal body and some being deposited polysilicon layers. It is, in general, not cost effective to maintain such surfaces in an oxygen free environment from the time that they are first formed until the contacting layer is in place. The latter is, most commonly, itself a layer of polysilicon.
Until recently, the presence of a layer of native oxide between the two silicon layers has not presented a serious problem because the area over which contact was made was large enough that the added series resistance of the native oxide layer was negligible and/or subsequent heat treatments required by the ongoing manufacturing process caused the layer to be short circuited. For example, phosphorus atoms, present in the polysilicon as a dopant, will, when heated to temperatures in excess of about 800.degree. C., break through the native oxide and reduce its resistance substantially.
With silicon processing now entering the so-called deep sub-micron era, both the above mechanisms (for neutralizing the effects of native oxide on contact resistance) are no longer present. The width of holes through which contact between the layers is to be made is now often less than about 0.35 microns and temperatures above 800.degree. C. are no longer used in process steps that follow deposition of the second layer.
The prior art does not appear to have addressed this problem yet. We note that Kuroi et al. in "Highly reliable 0.15 micron MOSFETs with surface proximity gettering (SPG) and nitrided oxide spacer using nitrogen implantation" in the 1995 Symposium on VLSI Technology Digest, pp. 19-20, describe how hot carrier degradation in MOSFETs can be suppressed by implanting nitrogen ions into the source and drain regions.
Tsai et al. (U.S. Pat. No. 5,648,287 July 1997) use nitrogen ion implantation as a self-aligning method to form oxidation barriers that are limited to the horizontal surfaces of an amorphous silicon layer used to coat an FET gate electrode. The amorphous silicon is then selectively oxidized on its vertical surfaces, thereby forming a secondary set of spacers for the gate.
Kobushi et al. (U.S. Pat. No. 4,897,368 January 1990) teach the use of an ultra-thin layer of silicon nitride, formed by nitrogen ion implantation, for the purpose of limiting grain boundary diffusion through a polycrystalline film.